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REV. 0
EVAL-AD1852EB
–4–
U8 (ADM811TART) is a RESET generator that provides
a debounced 200 ms reset signal from the push button (S3)
or on power up. The reset is active if the 5 V supply drops
below 3 V.
U7 (AD3303-5.0) is a low noise 5 V dc regulator for the ana-
log section of the AD1852.
U9 (OP275) is a low noise and distortion, audio op amp. U9
provides differential-to-single-ended conversion and a low-
pass anti-image filter. A third order low-pass Bessel filter
response is implemented with a –3 dB corner frequency of
100 kHz and a 60 dB/decade roll-off. This type of filter is
characterized by a linear phase response and fast transient
response without overshoot.
U10 (74HC00) is used to provide a reset code to the digital
interface receiver (U2), pins M0–3, at power up and also sends
the correct interface code to ensure the digital output for-
mat matches the input of the DAC.
U11 (74HC00) is used to select the correct master clock
source for the DAC when it is switched between the SPDIF
receiver (U2) and the Ext Data Interface (J2). A discrete logic
gate is used for this function, because of the excessive jitter
that modulates high-frequency clock signals when they are
handled by PLDs.
PERFORMANCE SPECIFICATIONS
Typical performance, for a sample rate of 48 kHz, is tabulated
below.
1. SNR, A-Weighted
2. DNR, A-Weighted
3. THD+N
4. Frequency Response
5. Noise Floor
6. Full-Scale Audio Output
–114 dBFS
±
1 dB
–114 dBFS
±
1 dB
–102 dBFS
±
2 dB
±
0.2 dB, 10 Hz to 20 kHz
–145 dBFS
2 V rms
ATTACHMENTS
The following is included for your convenience.
Appendix A: ABEL Source Code for Vantis MACH4-64/32
CPLD.
Appendix B: Set of Schematics, Figures 1 and 2.
Appendix C: PCB plots showing the silkscreen layer, top
signal layer, ground planes, power planes, and the bottom
signal layer, Figures 3–7.
FURTHER INFORMATION
Ordering information: order number is EVAL-AD1852EB.
For application questions, please contact our Central Applica-
tions Department at 1-781-937-1428 for assistance.
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